1. Technical Field
The present invention relates generally to a semiconductor device and a method for manufacturing the same, and more particularly to a technology for simplifying the process of manufacturing a semiconductor device and preventing a short between a storage node contact plug and a bit line.
2. Related Art
Semiconductor devices include a plurality of unit cells including a capacitor and a transistor. The capacitor is used to store data and the transistor is used to transfer data between the capacitor and a bit line in response to a control signal (a word line) using a semiconductor property in which electric conductivity changes according to conditions. The transistor has three parts: a gate, a source, and a drain. Charges move between the source and drain in response to the control signal input to the gate. The charges move between the source and drain through a channel region using semiconductor properties.
When a conventional transistor is fabricated on a semiconductor substrate, the gate is formed over the semiconductor substrate and then the source and drain are formed by implanting impurities into the semiconductor substrate. In this case, the area between the source and drain below the gate becomes the channel region of the transistor. A transistor having such a horizontal channel region occupies a given area of the semiconductor substrate. In complicated semiconductor memory devices, it is difficult to reduce overall size because a plurality of transistors are included in each semiconductor memory device.
However, if the size of the semiconductor memory device is reduced, the number of semiconductor memory devices that can be produced per wafer can be increased, thereby improving productivity. In order to reduce the size of the semiconductor memory device, various methods have been suggested. For example, instead of a conventional planar gate having a horizontal channel region, a recess gate may be used. A recess is formed in the semiconductor substrate, and a gate is formed in the recess so that a channel region may be formed along a curved surface of the recess.
A buried gate, obtained by burying the entire gate within the recess, has also been studied. In a semiconductor device including a buried gate, after the semiconductor substrate is etched to a given depth to form a trench, a gate electrode is buried in the trench, and then a bit line is formed over the semiconductor substrate. A storage node contact plug connected to the semiconductor substrate is formed at both sides of the bit line, and a storage electrode connected to the storage node contact plug may also be formed.
During the process for forming the storage electrode region, a hard mask layer disposed over the bit line may be lost, which results in weak electrical characteristics between two cells. In order to prevent this shortcoming, a process for forming an additional storage node contact plug coupled to the initial storage node contact plug has been suggested. However, the additional processes necessary for forming the double storage electrode contact plugs may increase production costs.
Moreover, such a structure may cause contact resistance to increase. In order to lower the interface resistance between the polysilicon layer disposed over the storage node contact plug and a TiN layer that comprises the lower contact of the storage electrode, a titanium layer is stacked after the storage electrode region is formed. As a result, an additional process for forming a titanium silicide (TixSi) is required, thus narrowing the size of the lower portion of the storage electrode region and reducing a margin of the subsequent process.